Accelerating Digital Cell Characterization Using Deep Learning

Presentation slides

Paper

Digital Integrated Circuits (IC) implement complex functions (e.g., multiplier, adder) as electrical circuits using interconnections of building blocks called cells. Cells implement Boolean functions as a network of transistors used as switches. Each circuit, such as adder, should compute its results within a certain time in order for its results to be used reliably by another circuit. During the design phase, the time taken by a circuit to compute its results is usually calculated using the delays of its constituent cells which are computed a priori. Computing delays of cells involves transistor-level simulations with all possible input event combinations. These simulations are computationally expensive.

This project introduces DeepSPICE, a machine learning approach to accelerate the characterization of the building blocks, or cells, of digital integrated circuits. In contrast to the current approach of computing the input-to-output propagation delays of a cell by simulating all possible input event combinations, the DeepSPICE approach is to train a Deep Neural Network (DNN) to learn relationships between events at the inputs of a cell and the corresponding output delays using a subset of transistor-level simulation results, and predict the delays for the remaining input event combinations for that cell.

The DNN for training and prediction is created using the Keras framework, and Python is used for automating the entire flow. The effectiveness of the DeepSPICE approach is demonstrated on 14 CMOS logic cells with the number of inputs ranging from 2 to 7. Simulations to create the training set for each cell are performed using the open source NGSPICE circuit simulator on their transistor-level circuit descriptions. Experiments using two different train:test ratios of 0.25:0.75 and 0.3:0.7 demonstrate the promise of reduction in time with DeepSPICE, especially for large cells where simulation costs are expensive. For cells with at least 6 inputs, DeepSPICE computes propagation delays for all input event combinations 2 to 2.2 times faster than baseline while limiting the error between 6.3% and 12.3%.

Future work is to explore ideas to reduce the error further and also apply this approach to predict power consumption of cells and delays of larger circuits.